74LS193 DATASHEET PDF

This circuit is a synchronous up down 4-bit binary counter. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs. 74LS Synchronous 4-Bit Binary Counter with Dual Clock. General Description. The DM74LS circuit is a synchronous up/down 4-bit binary counter. The DM74LS circuit is a synchronous up/down 4-bit binary counter. Synchronous operation is provided by hav- ing all flip-flops clocked simultaneously.

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Fairchild Semiconductor Electronic Components Datasheet.

74LS193 Datasheet

This feature allows the. The counter is fully programmable; that is, each output may be preset to either level by entering the desired data at the inputs while the load input is LOW. Both borrow and carry outputs. View PDF for Mobile. Synchronous operation is provided by hav.

Synchronous 4-Bit Binary Counter With Dual Clock

This feature allows the counters to be used as modulo-N dividers by simply modi- fying the count length with the preset inputs. This mode of operation eliminates the output counting.

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A clear input has been provided which, when taken to a high level, forces datqsheet outputs to the low level; independent of the count and load inputs. These counters were designed to be cascaded without the need for external circuitry. The counter is fully programmable; that is, each output may. These counters were designed to be cascaded without the.

The borrow output produces a pulse equal in width to the count down input when the counter underflows. The direction of counting is determined datssheet which.

Similarly, the carry output produces a pulse equal in width. The counters can then be easily cascaded by feeding the. The output will change independently of the count pulses. The direction of counting is determined by which count datazheet is pulsed while the other count input is held HIGH.

74LS Datasheet(PDF) – Hitachi Semiconductor

The borrow output produces a pulse equal in. The clear, count, and load inputs are buffered to lower the drive requirements of clock drivers, etc. Similarly, the carry output produces a pulse equal in width to the count down input when an overflow condition exists.

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The counters can then be easily cascaded by feeding the borrow and carry outputs to the count down and count up inputs respectively of the succeeding counter.

This mode of operation eliminates the output counting spikes normally associated with asynchronous ripple- clock counters. The outputs of the four master-slave flip-flops are triggered. A clear input has been provided which, when taken to a. Synchronous operation is provided by hav- ing all flip-flops clocked simultaneously, so that the outputs datasheeg together when so instructed by the steering logic.

The clear, count, and load. Both borrow and carry outputs are available to cascade both the up and down counting functions. The output will change. Features s Fully independent clear input s Synchronous operation s Cascading circuitry provided internally s Individual preset each flip-flop Ordering Code: